گروه فنی مهندسی آرکام

·         Mealy style state-machines implement best for  CPLDs.

·         Moore style state-machines implement better for FPGAs.

library ieee;

use ieee.std_logic_1164.all;

entity mealy_4s is

  port

  (

    clk              : in  std_logic;

    data_in     : in  std_logic;

    reset          : in  std_logic;

    data_out  : out  std_logic_vector(1 downto 0)

  );

end entity;

architecture rtl of mealy_4s is

  -- Build an enumerated type for the state machine

  type state_type is (s0, s1, s2, s3);

  -- Register to hold the current state

  signal state : state_type;

begin

  SYNC_STATE: process (clk, reset)

  begin

    if reset = '1' then

      state <= s0;

    elsif (rising_edge(clk)) then

      case state is

        when s0=>

          if data_in = '1' then

            state <= s1;

          else

            state <= s0;

          end if;

        when s1=>

          if data_in = '1' then

            state <= s2;

          else

            state <= s1;

          end if;

        when s2=>

          if data_in = '1' then

            state <= s3;

          else

            state <= s2;

          end if;

        when s3=>

          if data_in = '1' then

            state <= s3;

          else

            state <= s1;

          end if;

      end case;

    end if;

  end process;

  -- Determine the output based only on the current state

  -- and the input (do not wait for a clock edge).

  OUTPUT_DECODE: process (state, data_in)

  begin

    case state is

      when s0=>

        if data_in = '1' then

          data_out <= "00";

        else

          data_out <= "01";

        end if;

      when s1=>

        if data_in = '1' then

          data_out <= "01";

        else

          data_out <= "11";

        end if;

      when s2=>

        if data_in = '1' then

          data_out <= "10";

        else

          data_out <= "10";

        end if;

      when s3=>

        if data_in = '1' then

          data_out <= "11";

        else

          data_out <= "10";

        end if;

    end case;

  end process;

end rtl;

library ieee;

use ieee.std_logic_1164.all;

entity moore_4s is

  port

(

    clk              : in  std_logic;

    data_in     : in  std_logic;

    reset          : in  std_logic;

    data_out  : out  std_logic_vector(1 downto 0)

  );

end entity;

architecture rtl of moore_4s is

  -- Build an enumerated type for the state machine

  type state_type is (s0, s1, s2, s3);

  -- Register to hold the current state

  signal state   : state_type;

begin

  SYNC_STATE: process (clk, reset)

  begin

    if reset = '1' then

      state <= s0;

    elsif (rising_edge(clk)) then

      case state is

        when s0=>

          if data_in = '1' then

            state <= s1;

          else

            state <= s0;

          end if;

        when s1=>

          if data_in = '1' then

            state <= s2;

          else

            state <= s1;

          end if;

        when s2=>

          if data_in = '1' then

            state <= s3;

          else

            state <= s2;

          end if;

        when s3 =>

          if data_in = '1' then

            state <= s3;

          else

            state <= s1;

          end if;

      end case;

    end if;

  end process;

  -- Output depends solely on the current state

 OUTPUT_DECODE: process (state)

  begin

    case state is

      when s0 =>

        data_out <= "00";

      when s1 =>

        data_out <= "01";

      when s2 =>

        data_out <= "10";

      when s3 =>

        data_out <= "11";

    end case;

  end process;

end rtl;

A counter is a Moore machine ...

A counter is not a Mealy machine...

library ieee;

use ieee.std_logic_1164.all;

entity moore_4s is

  port

(

    clk              : in  std_logic;

    data_in     : in  std_logic;

    reset          : in  std_logic;

    data_out  : out  std_logic_vector(1 downto 0)

  );

end entity;

architecture rtl of moore_4s is

  -- Build an enumerated type for the state machine

  type state_type is (s0, s1, s2, s3);

  -- Register to hold the current state

  signal state, next_state  : state_type;

  signal data_out _i  :  std_logic_vector(1 downto 0);

begin

  NEXT_STATE_DECODE: process (state, data_in)

  begin

    next_state <= state;

      case state is

        when s0=>

          if data_in = '1' then

            next_state  <= s1;

          else

            next_state  <= s0;

          end if;

        when s1=>

          if data_in = '1' then

            next_state  <= s2;

          else

            next_state  <= s1;

          end if;

        when s2=>

          if data_in = '1' then

            next_state  <= s3;

          else

            next_state  <= s2;

          end if;

        when s3 =>

          if data_in = '1' then

            next_state  <= s3;

          else

            next_state  <= s1;

          end if;

      end case;

  end process;

  -- Output depends solely on the current state

  OUTPUT_DECODE: process (state)

  begin

    case state is

      when s0 =>

        data_out_i <= "00";

      when s1 =>

        data_out_i <= "01";

      when s2 =>

        data_out_i <= "10";

      when s3 =>

        data_out_i <= "11";

    end case;

  end process;

  SYNC_DATA: process (clk, reset)

  begin

    if  (rising_edge(clk)) then

      if reset = '1' then

        state <= s0;

        data_out <= "00"';

      else

        state <= next_state;

        data_out <= data_out_i;

      end if;       

    end if;

  end process;

end rtl;