ERROR:Place:1205

شماتیک تکنولوژی مدار پیاده سازی شده را بررسی کنید. باید یک چنین ساختاری را مشاهده کنید!

DCM --> BUFG --> OBUF

 

ERROR:Place:1205 - This design contains a global buffer instance,

<Inst_vga_pll/clkout3_buf>, driving the net, <clk_sdram>, that is driving the

following (first 30) non-clock load pins off chip.

< PIN: S_CLK.O; >

   This design practice, in Spartan-6, can lead to an unroutable situation due

to limitations in the global routing. If the design does route there may be

excessive delay or skew on this net. It is recommended to use a Clock

   Forwarding technique to create a reliable and repeatable low skew solution:

instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to

Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to

.C1. If you wish to override this recommendation, you may use the

   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote

this message to a WARNING and allow your design to continue. Although the net

may still not route, you will be able to analyze the failure in FPGA_Editor.

< PIN "Inst_vga_pll/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >

High Speed, Synchronous, Parallel Bus for Xilinx Spartan-6 FPGA‎

There is a dedicated clock routing structure named BUFIO2 for sampling input pins. The IOCLK output of the BUFIO2 MUST be used to drive the input pad flip-flop clock. The DIVCLK output of the BUFIO2 MUST be connected to a global clock buffer (BUFG) and is used to drive internal logic.

 

The BUFIO2s must be in the same half side of the device as the data pin being clocked.

 

The BUFIO2 takes a GCLK clock input and generates two clock outputs and a strobe pulse.

* IOCLK – normal output

* DIVCLK – divided output (by 1,2,3,4,5,6,7,8)

* SERDESSTROBE - clock network output used to drive IOSERDES2

 

The ODDR2 uses a clock and it's counter clock, so if the clock is really fast or has not a 50% duty cycle, use a PLL (DCM) for generating clock and not_clock.