There is a dedicated clock routing structure named BUFIO2 for sampling input pins. The IOCLK output of the BUFIO2 MUST be used to drive the input pad flip-flop clock. The DIVCLK output of the BUFIO2 MUST be connected to a global clock buffer (BUFG) and is used to drive internal logic.
The BUFIO2s must be in the same half side of the device as the data pin being clocked.
The BUFIO2 takes a GCLK clock input and generates two clock outputs and a strobe pulse.
* IOCLK – normal output
* DIVCLK – divided output (by 1,2,3,4,5,6,7,8)
* SERDESSTROBE - clock network output used to drive IOSERDES2
The ODDR2 uses a clock and it's counter clock, so if the clock is really fast or has not a 50% duty cycle, use a PLL (DCM) for generating clock and not_clock.
