entity dg612_ctrl is
generic
(
-- Many synthesis tools support only integer generics.
sw_on_g : integer := 50;
sw_off_g : integer := 50
);
Port
(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sw : out STD_LOGIC
);
end dg612_ctrl;
--==============================================================================--
architecture Behavioral of dg612_ctrl is
--==============================================================================--
-- An integer range 0 to N-1 synthesizes to a bus of width log2 N bits. The value
-- is represented as a binary number. Negative numbers are represented in two's
-- complement format.
signal sw_cnt : integer;
signal sw_i : std_logic;
...
