گروه فنی مهندسی آرکام

entity clk64khz is

    port (

        clk    : in  std_logic;    -- 50mhz

        reset  : in  std_logic;

        clk_out: out std_logic    -- 2khz

    );

end clk64khz;

architecture behavioral of clk64khz is

    signal temporal: std_logic;

    -- scaling factor = fin/fout = 25000

    signal counter : integer range 0 to 12499 := 0;

begin

    freq_divider: process (reset, clk) begin

        if (reset = '1') then

            temporal <= '0';

            counter  <= 0;

        elsif rising_edge(clk) then

            if (counter = 12499) then

                temporal <= not(temporal);

                counter  <= 0;

            else

                counter <= counter + 1;

            end if;

        end if;

    end process;

    clk_out <= temporal;

end behavioral;