شماتیک تکنولوژی مدار پیاده سازی شده را بررسی کنید. باید یک چنین ساختاری را مشاهده کنید!
DCM --> BUFG --> OBUF
ERROR:Place:1205 - This design contains a global buffer instance,
<Inst_vga_pll/clkout3_buf>, driving the net, <clk_sdram>, that is driving the
following (first 30) non-clock load pins off chip.
< PIN: S_CLK.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue. Although the net
may still not route, you will be able to analyze the failure in FPGA_Editor.
< PIN "Inst_vga_pll/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1136 - This design contains a global buffer instance,
<Inst_vga_pll/clkout3_buf>, driving the net, <clk_sdram>, that is driving the
following (first 30) non-clock load pins.
< PIN: S_CLK.O; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "Inst_vga_pll/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
با تنزل این خطا به یک هشدار! در واقع، فقط این مشکل را ماست مالی کرده اید! بعدا بوی گندش درمیاد!
Inst_ODDR2: ODDR2
generic map
(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset
)
port map
(
Q => clk_sdram, -- 1-bit output data
C0 => clk_sdram_i, -- 1-bit clock input
C1 => not clk_sdram_i, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
حالا، یک چنین ساختاری را داریم!
DCM --> BUFG -->ODDR2 --> OBUF
