گروه فنی مهندسی آرکام

wire

reg

wire elements are used to connect input and output ports of a module instantiation together with some other element in your design.

reg elements can be connected to the input port of a module instantiation.

reg elements cannot be connected to the output port of a module instantiation.

wire elements are used as inputs and outputs within an actual module declaration.

reg elements can be used as outputs within an actual module declaration.

reg elements cannot be used as inputs within an actual module declaration.

wire elements cannot be used as the left-hand side of an = or <= sign in an always@ block.

reg is the only legal type on the left-hand side of an always@ block = or <= sign.

wire elements are the only legal type on the left-hand side of an assign statement.

reg cannot be used on the left-hand side of an assign statement.

wire elements are a stateless way of connecting two pieces in a Verilog-based design.

reg can be used to create registers when used in conjunction with always@(posedge Clock) blocks.

wire elements can only be used to model combinational logic.

reg can be used to create both combinational and sequential logic

Both can appear on the right-hand side of assign statements and always@ block = or <= signs.

Both can be connected to the input ports of module instantiations.