گروه فنی مهندسی آرکام

input CLK_50MHz;

...

wire CLK_25MHz;

...

clock_divider clk_div(.clk_in(CLK_50MHz), .clk_out(CLK_25MHz));

...

...

module clock_divider(clk_in, clk_out);

                input clk_in;

                output clk_out;

                reg clk_out = 0;

                always @(posedge clk_in)

                                clk_out <= ~clk_out;

endmodule