گروه فنی مهندسی آرکام

clk_i : in  std_logic;

clk_o: out  std_logic;

...

signal clk : std_logic := '0';

...

clk_o <= clk;

...

process (clk)

begin

                if ( rising_edge (clk) ) then

                ...

                end if;

end process;

...

-- IBUFG: Global Clock Buffer (sourced by an external pin)

IBUFG_Inst : IBUFG

generic map ( IOSTANDARD => "default")

port map (o => clk, i => clk_i );