ADC1_DOUT_P : in std_logic_vector(11 downto 0);
ADC1_DOUT_N : in std_logic_vector(11 downto 0);
...
Loop1: for i in 0 to 11 generate
IBUFDS_inst1 : IBUFDS
generic map
(
CAPACITANCE => "DONT_CARE",
DIFF_TERM => TRUE
IBUF_DELAY_VALUE => "0
IFD_DELAY_VALUE => "AUTO
IOSTANDARD => "DEFAULT"
)
port map
(
O => adc1_dout_r1(i),
I => ADC1_DOUT_P(i),
IB => ADC1_DOUT_N(i)
);
end generate;
...
process(adc1_clkout)
begin
if(rising_edge(adc1_clkout)) then
adc1_dout_r2 <= adc1_dout_r1;
adc1_dout <= adc1_dout_r2;
end if;
end process;