گروه فنی مهندسی آرکام

Library IEEE;

  Use IEEE.std_logic_1164.All;

  Use IEEE.std_logic_arith.All;

  Use IEEE.std_logic_unsigned.All;

Entity rst_gen is

  Port(

    clk    : in  std_logic;

    reset    : out  std_logic

  );

End Entity;

Architecture bh of rst_gen is

  Signal counter : std_logic_vector( 7 Downto 0):=(others=>'0');

Begin

Process(clk)

  Begin

    If rising_edge(clk) Then

      If (counter = X"FF") Then

        reset <= '0';

      Else

        counter <= counter + 1;

        reset <= '1';

      End If;

    End If;

End Process;

End Architecture;