گروه فنی مهندسی آرکام

entity addr_gen is

  generic

  (

    C_MAX_DEPTH : integer := 1024 ;

    RST_VALUE   : std_logic_vector(31 downto 0) := (others=> '0');

    RST_INC     : integer := 0 -- offset

  );

  port

  (

    clk         : in std_logic;

    rst         : in std_logic;

    en          : in std_logic;

    load        : in std_logic;

    load_value  : in std_logic_vector (31 downto 0)  := (others => '0');

    addr_out    : out std_logic_vector (31 downto 0)

  );

end addr_gen;

architecture behavioral of addr_gen is

  signal addr_temp : std_logic_vector(31 downto 0) := (others =>'0');

begin

  addr_out <= addr_temp;

  process(clk)

  begin

    if(rising_edge(clk)) then

      if(rst='1') then

        addr_temp <= RST_VALUE + conv_std_logic_vector(RST_INC, 32);

      else

        if(en='1') then

          if(load='1') then

            addr_temp <= load_value;

          else

            if(addr_temp = C_MAX_DEPTH - 1) then

              addr_temp <= RST_VALUE + conv_std_logic_vector(RST_INC, 32);

            else

              addr_temp <= addr_temp + '1';

            end if;

          end if;

        end if;

      end if;

    end if;

  end process;

end architecture;