entity random is
generic
(
WIDTH : integer := 32;
SEED : integer := 2
);
port
(
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
random_num : out std_logic_vector (WIDTH-1 downto 0) --output vector
);
end random;
architecture behavioral of random is
begin
process(clk)
variable rand_temp : std_logic_vector(WIDTH-1 downto 0):= conv_std_logic_vector(SEED, WIDTH);
variable temp : std_logic := '0';
begin
if(rising_edge(clk)) then
if(rst='1') then
rand_temp := conv_std_logic_vector(SEED, WIDTH);
else
if(en = '1') then
temp := rand_temp(WIDTH-1) xor rand_temp(WIDTH-2);
rand_temp(WIDTH-1 downto 1) := rand_temp(WIDTH-2 downto 0);
rand_temp(0) := temp;
end if;
end if;
end if;
random_num <= rand_temp;
end process;
end architecture;
