A CAN interface board for the PCI bus...
CAN Controller: SJA1000 from Philips, with 64-byte receive FIFO...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity sja1000_can_ctrl is
port
(
clk : in std_logic;
rst : in std_logic;
CAN_INTL : in std_logic;
CAN_AD : inout std_logic_vector(7 downto 0);
CAN_ALE : out std_logic;
CAN_CSL : out std_logic;
CAN_RDL : out std_logic;
CAN_WRL : out std_logic;
CAN_RSTL : out std_logic;
can_baud_rate : in std_logic_vector(1 downto 0);
can_data_strb : in std_logic;
can_data : out std_logic_vector(15 downto 0);
can_data_rdy : out std_logic;
can_error_id : out std_logic_vector(7 downto 0);
can_servo_type : out std_logic;
can_servo_error : out std_logic_vector(1 downto 0);
can_disconnect : out std_logic
);
end sja1000_can_ctrl;
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architecture Behavioral of sja1000_can_ctrl is
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...
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begin
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CAN_RSTL <= not rst;
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...
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--Before setting up registers of the SJA1000, the host controller should check by
--reading the reset mode/request flag, if the SJA1000 has reached the reset mode,
--because the registers, which get the configuration information, can be written
--only during reset mode.
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--After power-on the SJA1000 is set into reset mode!
--After power-on the SJA1000 is in BasicCAN mode!
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end Behavioral;
