module address_generator
#(
ADDR_WIDTH = 10,
ADDR_TOP = 1000
)
(
clk,
rst,
clk_en,
sof,
addr
);
input clk, rst, clk_en;
input sof;
output reg [ADDR_WIDTH - 1: 0] addr;
always @ (posedge clk) begin
if (rst) begin
addr <= 0;
end else begin
if (sof) begin
addr <= 1;
end else begin
if (addr == ADDR_TOP)
addr <= 0;
addr <= addr + 1;
end
end
end
endmodule
