گروه فنی مهندسی آرکام

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;

use UNISIM.vcomponents.all;

--==============================================================================--

entity ltc2242_adc_ctrl is

    Port

    (

        ADC1_DOUT_P          : in std_logic_vector(11 downto 0);

        ADC1_DOUT_N          : in std_logic_vector(11 downto 0);

        ADC1_OF_P            : in std_logic;

        ADC1_OF_N            : in std_logic;

        ADC1_CLKOUT_P        : in std_logic;

        ADC1_CLKOUT_N        : in std_logic;

        adc1_dout            : out std_logic_vector(11 downto 0);

        clk1_240mhz          : out std_logic;

    );

end ltc2242_adc_ctrl;

--==============================================================================--

...

    Loop1: for i in 0 to 11 generate

        IBUFDS_inst1 : IBUFDS

        generic map

        (

            CAPACITANCE      => "DONT_CARE",

            DIFF_TERM        => TRUE,

            IBUF_DELAY_VALUE => "0",

            IFD_DELAY_VALUE  => "AUTO",

            IOSTANDARD       => "DEFAULT"

        )

        port map

        (

            O                => adc1_dout_r1(i),

            I                => ADC1_DOUT_P(i),

            IB               => ADC1_DOUT_N(i)

        );

    end generate;

...