library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
--==============================================================================--
-- An entity contains a port that defines all inputs and outputs to a file.
entity srf05_ctrl is
port
(
clk : in STD_LOGIC;
trig : out STD_LOGIC;
echo : in STD_LOGIC;
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
-- Std_logic is the type that is most commonly used to define signals, but there
-- are others that you will learn about...
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
distance : out STD_LOGIC_VECTOR(8 downto 0)
);
end srf05_ctrl;
...