گروه فنی مهندسی آرکام

-- 64-Bit by 32-Bit Division

entity div64 is

  port

  (

    rst_n    : in  std_logic; -- Active Low

    clk      : in  std_logic;   

    -- Asserting the HOLD input at any time will freeze the operation, until HOLDN is de-asserted.

    holdn    : in  std_logic; -- Active Low

    op1      : in  std_logic_vector(64 downto 0); -- operand 1 (dividend)

    op2      : in  std_logic_vector(32 downto 0); -- operand 2 (divisor)

    flush    : in  std_logic; -- Flush current operation - Active High

    signed   : in  std_logic; -- Signed division - Active High

    start    : in  std_logic; -- The division is started when '1' is samples on START on positive clock edge.     

    ready    : out std_logic; -- The division operation takes 36 clock cycles

--   

-- Condition codes

--

-- ICC[3] - Negative result

-- ICC[2] - Zero result

-- ICC[1] - Overflow

-- ICC[0] - Not used. Always '0'

--

    icc      : out std_logic_vector(3 downto 0); -- ICC - Negative result, zero result and overflow are detected

--

-- Divide Overflow Detection and Value Returned

--

-- unsigned quotient > 2**31-1 --> result = 0xffffffff

-- positive quotient > 2**31-1 --> result = 0x7fffffff

-- negative quotient > 2**31-1 --> result = 0x80000000

--

    result   : out std_logic_vector(31 downto 0) -- div result - The result is rounded towards zero   

    -- The divider leaves no remainder.

);

end;

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