...
u08 ads7809Init(void)
{
// initialize spi interface
spiInit();
/* External DATACLK = 100kHz ~ 10MHz */
// switch to f/4 bitrate
cbi(SPCR, SPR0);
cbi(SPCR, SPR1); // SPI Clock Rate: 2MHz
// sbi(SPSR, SPI2X);
// setup clock
/*
If EXT/INT is HIGH, data will be output synchronized
to the clock input on DATACLK.
*/
sbi(ADS7809_CKS_DDR, ADS7809_CKS_PIN);
sbi(ADS7809_CKS_PORT, ADS7809_CKS_PIN); // External Clock
...
...
u08 ad7927Init(void)
{
// initialize spi interface
spiInit();
// switch to f/4 bitrate
cbi(SPCR, SPR0);
cbi(SPCR, SPR1);
// setup chip select
sbi(AD7927_CS_PORT, AD7927_CS_PIN);
sbi(AD7927_CS_DDR, AD7927_CS_PIN);
// Set write bit, power mode normal, range 0-5V, coding straight binary
ad7927ctrlreg = (1<<AD7927_WRITE)|(1<<AD7927_PM1)|(1<<AD7927_PM0)|(1<<AD7927_CODING);
ad7927WriteCtrlReg(ad7927ctrlreg);
// return success
return 1;
}
...
...
u08 ad5664Init(void)
{
// initialize spi interface
spiInit();
// switch to f/4 bitrate
cbi(SPCR, SPR0);
cbi(SPCR, SPR1);
// setup chip select
sbi(AD5664_CS_PORT, AD5664_CS_PIN);
sbi(AD5664_CS_DDR, AD5664_CS_PIN);
ad5664cmd = AD5664_CMD_IREF;
ad5664data = AD5664_IREF_ON;
ad5664WriteShftReg();
// return success
return 1;
}
...
WARNING:HDLCompiler:751
Re-declaration of ANSI port x is not allowed
The outputs of a primitive, internally can be of type net or reg, externally the outputs MUST be connected to a variable of type net.
برای اتصال خروجی (Net) بیرونی یک زیرماژول به ورودی (Net / Reg) بیرونی زیرماژول دیگر و خروجی (Net / Reg) درونی ماژول اصلی (Top) نیازی به تعریف یک Wire دیگر نداریم ...! چی گفتم!
WARNING:HDLCompiler:946
Actual for formal port x is neither a static name nor a globally static expression
یعنی! استاتیک نیست! متغیر است!
In a port map NO functions SHOULD be used!
این محدودیت در Verilog وجود ندارد!
***Note: ISE Design Suite does not support VHDL 2008.
شماتیک تکنولوژی مدار پیاده سازی شده را بررسی کنید. باید یک چنین ساختاری را مشاهده کنید!
DCM --> BUFG --> OBUF
ERROR:Place:1205 - This design contains a global buffer instance,
<Inst_vga_pll/clkout3_buf>, driving the net, <clk_sdram>, that is driving the
following (first 30) non-clock load pins off chip.
< PIN: S_CLK.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue. Although the net
may still not route, you will be able to analyze the failure in FPGA_Editor.
< PIN "Inst_vga_pll/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
Three primary delivery methods exist to program an SPI serial flash through the SPI interface:
*Third-party programmers (off-board programming)
* Indirect in-system programming (JTAG tool vendor or custom solution)
* Direct in-system programming (SPI direct interface connect)
The ISE Suite iMPACT tool version 11.4 is the last supported release for DIRECT in-system SPI programming. For new designs, the iMPACTINDIRECT in-system SPI programming solution is recommended. This solution uses a single JTAG connection to both configure theFPGA and indirectly program the flash.
*PROG_B should be held Low during the direct programming of the SPI serial flash.
*PROG_B can be driven Low to High with external logicto reconfigure the FPGA.
iMPACT Project Wizard >Configuredevices > using Direct SPI Configuration mode
Comparison of Spartan-3 and Spartan-6, which seems to be the same size!
|
Manufacturer Part Number |
Number of LABs/CLBs |
Number of Logic Elements/Cells |
Total RAM Bits |
Number of I/O |
|
XC3S400-4TQG144I |
896 |
8064 |
294912 |
97 |
|
XC6SLX9-2TQG144I |
715 |
9152 |
589824 |
102 |
* Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops.
* Up to 1050Mb/s data transfer rate per differential I/O.
* Each slice contains a fast 18 x 18 multiplier and a 48-bit accumulator capable of operating at 390MHz.
* 18Kb blocks can be split into two independent 9Kb block RAMs.
* To use LVCMOS25 inputs when VCCO is NOT 2.5V, VCCAUX must be set to 2.5V.
* The IODELAY2 can only be used in Variable Mode to delay inputs. When using the IODELAY2 with an output, it can only be used in FIXED delay mode.
* There is NO memory controller on the XC6SLX9 in the TQG144 package.
* That BPI configuration is NOT supported in the XC6SLX4, XC6SLX25, and XC6SLX25T nor is BPI available when using Spartan-6 FPGAs in TQG144 and CPG196 packages.
ERROR:HDLCompiler:410 - ".vhd" Line xx: Expression has x elements; expected y"
libraryieee;
use ieee.std_logic_1164.all;
useieee.numeric_std.all;
...
constant K : integer := 128;
...
variable r : signed(31 downto 0);
variable d : signed(31 downto 0);
...
r := resize(r + (K * d), 32)
برای کارهای کنترلی از Std_logic_arith و برای کارهای پردازشی (محاسباتی) از Numeric_std استفاده کنید...
هرگز از هر دوی این پکیج ها در یک فایل استفاده نکنید! (ERROR:HDLCompiler:607)! قبلاًها! روی FPGAهای قدیمی تر امکانش بود! اما اصلا کار درستی نبود! از ما گفتن بود!
استفاده از Numeric_std، شما را مجبور می کند!!! تا نوع داده را از نظر علامت دار یا بی علامت مشخص کنید... تا خروجی مناسب با نتایج Matlab برای شما حاصل شود...
$ cd risinghf/test/
$ ./test_loragw_reg
...
End of register verification
IMPLICIT_PAYLOAD_LENGHT = 0 (should be 197)
FRAME_SYNCH_PEAK2_POS = 0 (should be 11)
PREAMBLE_SYMB1_NB = 0 (should be 49253)
ADJUST_MODEM_START_OFFSET_SF12_RDX4 = 0 (should be 3173)
IF_FREQ_1 = 0 (should be -1947)
End of test for loragw_reg.c
IDT7202: Async FIFO 1,024 x 9
M25P80: 8 Mbit Serial Flash Memory with 75MHz SPI Bus Interface
M25P128: 128 Mbit Serial Flash Memory with 54MHz SPI Bus Interface
S25FL064A: 64 Mbit Serial Flash Memory with 40MHz SPI Bus Interface
-- 64-Bit by 32-Bit Division
entity div64 is
port
(
rst_n : in std_logic; -- Active Low
clk : in std_logic;
-- Asserting the HOLD input at any time will freeze the operation, until HOLDN is de-asserted.
holdn : in std_logic; -- Active Low
op1 : in std_logic_vector(64 downto 0); -- operand 1 (dividend)
op2 : in std_logic_vector(32 downto 0); -- operand 2 (divisor)
flush : in std_logic; -- Flush current operation - Active High
signed : in std_logic; -- Signed division - Active High
start : in std_logic; -- The division is started when '1' is samples on START on positive clock edge.
ready : out std_logic; -- The division operation takes 36 clock cycles
--
-- Condition codes
--
-- ICC[3] - Negative result
-- ICC[2] - Zero result
-- ICC[1] - Overflow
-- ICC[0] - Not used. Always '0'
--
icc : out std_logic_vector(3 downto 0); -- ICC - Negative result, zero result and overflow are detected
--
-- Divide Overflow Detection and Value Returned
--
-- unsigned quotient > 2**31-1 --> result = 0xffffffff
-- positive quotient > 2**31-1 --> result = 0x7fffffff
-- negative quotient > 2**31-1 --> result = 0x80000000
--
result : out std_logic_vector(31 downto 0) -- div result - The result is rounded towards zero
-- The divider leaves no remainder.
);
end;
...
-- A recursive moving average calculation is given as
-- y[n] = y[n - 1] + (x[n] - x[n - N]) / N
-- which is easily implemented in digital logic (again with the caveat that N is
-- restricted to powers-of-two), but requires additional block RAM resources that
-- are otherwise not necessary in a simple arithmetic mean.
--==============================================================================--
entity moving_average is
GENERIC
(
DATA_W : integer := 32;
MAX_POINTS : integer := 64;
SCALING_BY_2 : integer := 0;
N_W : integer := integer(ceil(log2(real(MAX_POINTS))))
);
PORT
(
reset_n : in std_logic;
clk : in std_logic;
N : in std_logic_vector(N_W downto 0);
valid_in : in std_logic;
x : in std_logic_vector(DATA_W-1 downto 0);
valid_out : out std_logic;
y : out std_logic_vector(DATA_W-1 downto 0)
);
end moving_average;
--==============================================================================--
...https://www1.qt.io/offline-installers/?hsLang=en
https://download.qt.io/archive/qt/5.8/5.8.0/qt-opensource-windows-x86-msvc2015_64-5.8.0.exe
5.6 and 5.9 as LTS versions they are supported for three years.
The EASIEST (FIRST) WAY to access the X11 window system is to call up the initialization program xinit from the console. Then, the xinit analyzes the contents of $HOME/.xinitrc and starts commands entered there in sequence, analogously to shell scriptprocessing.
If the ~HOME/.xinitrc configuration file does not exist,xinit opens a command interpreter (xterm)...
xterm -geometry +1+1 -n login -display :0
* The -geometry +1+1 option has the effect that the leftcorner of the xterm window on the upper picture margin ispositioned one pixel down and to the right...
* The -n loginoption assignsthe name login to the window...
* The display: 0option causes xinitto present the window on the local X server...
رضا مهربانی! دیروز متوجه شدم حتی نمی دونه بادریت چیه! کن چیه ... یه کد اُورد .. گفت این کد C# خودم زدم ... مثل ... دروغ میگه ... دوست داشتم اون جلو آمپر کنم تو دهانش ... اما ...
WARNING:Place:1109: - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. ... There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR ....
از کنار این هشدار به سادگی نگذرید! خیلی خیلی مهم است ... انتظار نداشته باشید که با وجود این خطا، برنامه تان به درستی کار کند ... شاید هم مجبور شوید PCB تان را دوباره طراحی کنید ...
در این پروژه تصویر دوربین OV7670 با استفاده از VGA روی مانیتور نمایش داده می شود.
* واحد vga_pll تولید کلاک های 50MHz و 25MHz را برعهده دارد. کلاک 25MHz برای واحد VGA و کلاک 50MHz برای سایر واحد ها استفاده می شود. فریم های تصویر از سنسور با کلاک 50MHz دریافت می شود.
* واحد ov7670_controller وظیفه مدیریت و کنترل سنسور ov7670، تولید کلاک و سیگنال و تنظیم رجیسترهای سنسور را بر عهده دارد.
* واحد ov7670_capture دریافت داده های سنسور را انجام می دهد. داده های سنسور از یک پورت 8 بیتی دریافت می شود. اطلاعات یک پیکسل شامل 12 بیت است که این داده ها در طول دو مرحله از سنسور ارسال می شود. این واحد وظیفه دارد در ابتدا پیکسل تصویر را پیدا کرده و بعد از آن با تولید آدرس، اطلاعات پیکسل های دریافتی را در یک حافظه رم دو پورت ذخیره کند.
* واحد address_generator وظیفه دارد آدرس مناسب برای خواندن از حافظه رم دو پورت را تولید کند و به واحد RGB ارسال کند.
* واحد RGB در کنار واحد VGA وظیفه تولید سیگنال های تصویر خروجی روی پورت VGA را برعهده دارند.
PhysDesignRules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
Other Map Command Line Options
-convert_bram8
...
Other Bitgen Command Line Options
-g INIT_9K:Yes
