The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC).
entity ad9648_adc_ctrl is
port
(
clock_in : in std_logic;
adc_a : in std_logic_vector(13 downto 0);
adc_b : in std_logic_vector(13 downto 0);
adc_sdio : out std_logic;
adc_sclk : out std_logic;
adc_csb : out std_logic;
adc_oeb : out std_logic;
adc_pdwn : out std_logic;
adc_clk_p : out std_logic;
adc_clk_n : out std_logic
);
end ad9648_adc_ctrl;
...
adc_clk_p <= clk_100m_n;
adc_clk_n <= clk_100m_p;
...
process(clk_100m)
begin
if rising_edge(clk_100m) then
adca_data <= adc_a_delayed;
adcb_data <= adc_b_delayed;
adca_data_buf <= std_logic_vector(resize(signed(adca_data), adca_data_buf'length));
adcb_data_buf <= std_logic_vector(resize(signed(adcb_data), adcb_data_buf'length));
end if;
end process;
IODELAY: Input and Output Fixed or Variable Delay Element
This design element can be used to provide a Fixed Delay or an Adjustable Delay to the input path and a fixed delay for the output path of the Spartan-6 FPGA.
This delay can be useful for Data Alignment of incoming or outgoing data to/from the chip.
